A low voltage metal oxide semiconductor (LV MOS) device is a low on resistance and low voltage transistor whereby low voltages may be supplied by a microcontroller or a mechanical switch, for example. In a non-limiting example, high powered devices may be controlled by low power control mechanisms that can be provided by a low voltage metal oxide semiconductor field effect transistor (LV MOSFET). The threshold voltages of other MOSFET devices are higher requiring a high voltage to trigger the circuit to provide a state to the controlled device. A MOS transistor may be an n-channel metal oxide semiconductor (nMOS) transistor or p-channel metal oxide semiconductor (pMOS) transistor.
Generally, a MOS transistor may have three modes of operation depending upon the terminal voltages. For example, a MOS transistor has terminal voltages Vg (gate terminal voltage), Vs (source terminal voltage), and Vd (drain terminal voltage). The MOS operates in a cutoff mode when a bias voltage Vgs between the gate and the source is less than the threshold voltage Vth of the MOS transistor. Essentially, in the cutoff mode, no channel develops and the current Ids in the channel region is zero.
In a preferred mode of operation, the MOS operates in a linear mode when the bias voltage Vgs exceeds the threshold voltage Vth as long as a channel voltage Vds does not exceed a saturation voltage Vds,sat. Typically, the saturation voltage is defined as the bias voltage Vgs that exceeds the threshold voltage Vth. The current Ids increases with the channel voltage Vds when the MOS is in the linear mode. Finally, the channel pinches off and the current saturates when the channel voltage Vas exceeds the saturation voltage Vds,sat. Ids is independent of Vds when the MOS transistor is in this saturation mode.
A LV MOS may generally be characterized by a reduced relative high specific on resistance (RON) in comparison to a high voltage metal oxide semiconductor (HV MOS) devices. Without intending to be limiting, conventional devices that have improved specific RON result in a degradation in the breakdown voltage. For example, short channel designs that may provide such an effect, can also induce punch through. Thus, conventional changes in the design of the MOS transistor that increase the breakdown voltage tend to also increase the RON. There remains a need in the art for a LV MOS design having a reduced but well-defined RON.
Additionally, there remains a need in the art to reduce the RON without substantially changing a desired breakdown voltage of the MOS transistor. Further, a long-felt need in the art has been to further reduce the size of low voltage semiconductor devices still having distinct but reduced leakage current at breakdown while maintaining a distinct, well defined response to ensure rapid switching speed in changing the state of the device being controlled by the LV MOS device.